Pass transistor DC characteristics

Most of the logic in digital VLSI circuits is made using CMOS logic because of its low power consumption, high fanout. But there are some circuits which are made using other logics like pass transistor logic, dynamic CMOS logic etc. Though these comprise a small part of the  VLSI circuit it is necessary to understand them. In this post we will be learning about the operation and DC characteristics of pass transistor logic(PTL).

First we will see a 2x1 multiplexer design using PTL. PTL can be implemented using only NMOS or only PMOS transistors.We use NMOS PTL because the mobility of NMOS devices is more than that of the PMOS devices.Then we will understand the operation and DC characteristics of both NMOS and PMOS PTL.

2x1 Multiplexer using PTL

Truth table and output equation of 2X1 multiplexer is shown below. Now when the select line is 1 , input I1 is to be selected and when select line is 0, input I0 is to be selected as output. The main difference between a CMOS logic and PTL is that in CMOS all the inputs are connected to gate terminal only. while in PTL the inputs are connected to source terminals of the transistor. 

By connecting the select line to gate terminal and I1 to the source terminal of an NMOS transistor then the second line of truth table is implemented at the drain terminal of NMOS. To implement the first line we need inverted signal of select line so we invert it using an inverter and then connect it to the gate terminal and I0 to the source terminal of another transistor. when we connect the drain terminals of both transistors we can see that it works as a 2X1 multiplexer.

DC characteristics of PTL

DC characteristics of single NMOS/PMOS transistor:

When an NMOS transistor gate terminal is connected to VDD and the source terminal is connected to VDD the voltage at drain terminal is VDD-Vtn. This effect is called threshold drop. This happens because for an NMOS transistor to operate in on-state Vgs should be greater than Vtn. Since the source and drain terminals are identical in a FET, source and gate are at same potential so the transistor thinks that the drain terminal is its source and starts conducting. When the voltage at drain terminal tries to increase beyond VDD-Vtn transistor thinks that its Vgs is getting lessthan Vtn and the stops conducting. 

But this threshold drop will not happen when we try to drive a 0 at the source terminal. Because since the Vgs is already greater than Vtn the transistor will always be in conduction state and the entire 0 will be passed to drain terminal.

Similarly one can explain the operation of PMOS pass-transistor. PMOS can pass a 1 completely while it cannot pass a 0 completely(Vtp is produced at drain). An important point to note from here is that NMOS cannot drive a 1 completely and PMOS cannot drive a 0 completely. Because of this reason in CMOS logic the pull-down network is made using NMOS transistors and pull-up network is made using PMOS transistors.

DC characteristics of multiple NMOS/PMOS transistor:

When two NMOS are connected in series normally we expect that as we keep on addeing a transistor to the series network the voltage will drop by Vtn every time. But this does not happen because as shown in figure-3 at node A the voltage is VDD-Vtn and now this becomes the source voltage of second transistor. The second transistor now have enough Vtn difference between its gate and source terminals so the drain will charge completely to VDD-Vtn and no further drop will be seen. So no matter howmany transistors are added in series the output will be only one Vtn drop from input voltage.

Now if we connect the drain output to another NMOS gate terminal as shown in figure-4, the output voltage drops by another threshold voltage. The concept here is same since the gate terminal of second NMOS have a voltage of VDD-Vtn its drain output can only go till VDD-Vtn which is a threshold voltage less than its gate voltage. The main drawback with PTL is that the output of a logic cannot be connected as control input to other logic as the voltage levels keep degrading by a threshold every time.

The same analysis applies for PMOS PTL also. In practical designs only NMOS PTL is used. Threshold drop and DC characteristics of multiple NMOS/PMOS transistors are very important concepts.Go to CMOS inverter DC characteristics for a clear understanding of how a CMOS inverter operates.